ADF4117

Features:

ADF4116: 550 MHz
ADF4117: 1.2 GHz
ADF4118: 3.0 GHz
2.7 V to 5.5 V Power Supply
Separate VP Allows Extended Tuning Voltage in 3 V Systems
Selected Charge Pump Currents
Dual Modulus Prescaler
ADF4116: 8/9
ADF4117/ADF4118: 32/33
3-Wire Serial Interface
Digital Lock Detect
Power-Down Mode
Fast Lock Mode




Application

Base Stations for Wireless Radio (GSM, PCS, DCS,CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment




Pinout








Specifications

AV_DD to GND³. . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
AV_DD to DV_DD . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V
V_P to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V to +7 V
V_P to AVDD . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . 0.3 V to V_DD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . 0.3 V to V_P + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . 40°C to +85°C
Storage Temperature Range . . . . . . . . . . 65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP _JA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
CSP _JA Thermal Impedance
(Paddle Soldered) . . . . . . . . . . . . . . . . . . . . . . . . .122°C/W
(Paddle Not Soldered) . . . . . . . . . . . . . . . . . . . . . .216°C/W






Description

The ADF4116 family of frequency synthesizers can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. ADF4116 family  consist of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters and a dual-modulus prescaler (P/P+1). The A (5-bit) and B (13-bit) counters, in conjunction with the dual modulus prescaler (P/P+1), implement an N divider (N = BP+A). In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator).

Control of all the on-chip registers is via a simple 3-wire interface. ADF4116 family operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use.