Features: ·Digital calibration via internal EEPROM·Supports SSI specification·Comprehensive fault detection·Reduced component count on secondary side·Standalone or microcontroller control·Generates error signal for primary-side PWM·Output voltage adjustment and margining·Current sharing·Current li...
ADM1041: Features: ·Digital calibration via internal EEPROM·Supports SSI specification·Comprehensive fault detection·Reduced component count on secondary side·Standalone or microcontroller control·Generates ...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Parameter | Rating |
Supply Voltage (Continuous), VDD | 6.5 V |
Data Pins SDA, SCL, VDATA | VDD + 0.5 V, GND − 0.3 V |
Continuous Power at 25°C, P D-QSOP24 | 450 mW |
Operating Temperature, TAMB | −40°C to +85°C |
Junction Temperature, TJ | 150°C |
Storage Temperature, TSTG | −60°C to +150°C |
Lead Temperature (Soldering, 10 Seconds), TL |
300°C |
ESD Protection on All Pins, VESD | 2 kV |
Thermal Resistance, Junction to Air, JA | 150°C/W |
ICT Source Current1 | 7 mA |
The ADM1041 is a secondary-side and management IC specifically designed to minimize external component counts and to eliminate the need for manual calibration or adjustment on the secondary-side controller. The principle application of this IC is to provide voltage control, current share, and housekeeping
functions for single output in N+1 server power supplies.
The ADM1041 is manufactured with a 5 V CMOS process and combines digital and analog circuitry. An internal EEPROM provides added flexibility in the trimming of timing and voltage and selection of various functions. Programming is done via an SMBus serial port that also allows communication capability
with a microprocessor or microcontroller.
The usual configuration using this ADM1041 IC is on a one per output basis. Outputs from the IC can be wire-ORed together or bused in parallel and read by a icroprocessor. A key feature on this IC is support for an OrFET circuit when higher efficiency or power density is required.