ADS4616A4A

The ADS4616A4A are two-bank Synchronous DRAMs organized as 524,288 words x 16 bits x 2 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications