Features: · Maximum Sample Rate: 65MSPS· 12-Bit Resolution· No Missing Codes· Total Power Dissipation Internal Reference: 660mW External Reference: 594mW· CMOS Technology· Simultaneous Sample-and-Hold· 70.8dBFS SNR at 10MHz IF· 3.3V Digital/Analog Supply· Serialized LVDS Outputs· Integrated Frame ...
ADS5242: Features: · Maximum Sample Rate: 65MSPS· 12-Bit Resolution· No Missing Codes· Total Power Dissipation Internal Reference: 660mW External Reference: 594mW· CMOS Technology· Simultaneous Sample-and-Ho...
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| Supply Voltage Range, AVDD Supply Voltage Range, LVDD Voltage Between AVSS and LVSS Voltage Between AVDD and LVDD Voltage Applied to External REF Pins All LVDS Data and Clock Outputs Analog Input Pins(2) Operating Free-Air Temperature Range, TA Lead Temperature, 1.6mm (1/16" from case for 10s) Junction Temperature Storage Temperature Range |
0.3V to +3.8V 0.3V to +3.8V 0.3V to +0.3V 0.3V to +0.3V 0.3V to +2.4V 0.3V to +2.4V 0.3V to min. [3.3V, (AVDD + 0.3V)] 40°C to +85°C +260°C +105°C 65°C to +150°C |
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported.
(2) The DC voltage applied on the input pins should not go below 0.3V. Also, the DC voltage should be limited to the lower of either 3.3V or (AVDD + 0.3V). If the input can go higher than +3.3V, then a resistor greater than or equal to 25W should be added in series with each of the input pins. Also, the duty cycle of the overshoot beyond +3.3V should be limited. The overshoot duty cycle can be defined either as a percentage of the time of overshoot over a clock period, or over the entire device lifetime. For a peak voltage between +3.3V and +3.5V, a duty cycle up to 10% is acceptable. For a peak voltage between +3.5V and +3.7V, the overshoot duty cycle should not exceed 1%. Any overshoot beyond +3.7V should be restricted to less than 0.1% duty cycle, and never exceed +3.9V.
The ADS5242 is a high-performance, 65MSPS, 4-channel analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size.
An integrated phase lock loop (PLL) multiplies the incoming ADC sampling clock by a factor of 12. This high-frequency LVDS clock is used in the data serialization and transmission process. The word output of each internal ADC is serialized and transmitted either MSB or LSB first. In addition to the four data outputs, a bit clock and a word clock are also transmitted. The bit clock is at 6x the speed of the sampling clock, whereas the word clock is at the same speed of the sampling clock. The ADS5242 provides internal references, or can optionally be driven with external references. Best performance can be achieved through the internal reference mode. ADS5242 is available in an HTQFP-64 PowerPAD package and is specified over a 40°C to +85°C operating range.