Features: PERFORMANCE:• Polynomial complies to Intelsat IESS-308; RTCA DO-217 Appendix F, Revision D and proposed ITU-TS SG-18 (Formerly CCITT SG- 18) Standards• 6 MBytes/sec burst transfer rate with a 6 MHz clock for all block lengths• Maximum channel rate of 1.5 MBytes/sec cont...
AHA4012B: Features: PERFORMANCE:• Polynomial complies to Intelsat IESS-308; RTCA DO-217 Appendix F, Revision D and proposed ITU-TS SG-18 (Formerly CCITT SG- 18) Standards• 6 MBytes/sec burst trans...
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PERFORMANCE:
• Polynomial complies to Intelsat IESS-308; RTCA DO-217 Appendix F, Revision D and proposed ITU-TS SG-18 (Formerly CCITT SG- 18) Standards
• 6 MBytes/sec burst transfer rate with a 6 MHz clock for all block lengths
• Maximum channel rate of 1.5 MBytes/sec continuous for block lengths from 54 bytes through 255 bytes using a 6 MHz clock
• Processing latency time less than 101 msec in continuous operation for block lengths of 100 bytes
FLEXIBILITY:
• Programmable to correct from 1 to 10 error bytes or 20 erasure bytes per block
• Block lengths programmable from 3 to 255 bytes
• Encode, decode or pass-through capability inline with data flow
• Continuous or burst mode operation
• Programmable error threshold to help determine channel performance
SYSTEM INTERFACE:
• Byte wide synchronous I/O ports with internal buffering on both ports
• Input data pins used for programmable parameters
• Dedicated control pins permit discontinuities in system data flow
OTHERS:
• 44 pin PLCC; 50 mil lead pitch
• Pin and plug compatible with the higher performance AHA4011
• Software emulation of the algorithm available
Symbol | Characteristic | Min | Max | Units | Test Conditions |
Tstg | Storage temperature | -55 | 150 | deg C | |
Vdd | Supply voltage | -0.5 | 6.0 | V | |
Vin | Input voltage | Vss-0.5 | Vdd+0.5 | V | |
Package: 44-pin PLCC (JEDEC Standard) |
The AHA4012B is a single chip integrated circuit that implements a Reed-Solomon Forward Error Correction algorithm. The AHA4012B is the lowest cost member of the AHA PerFECÔ family of forward error correction (FEC) devices conforming to the Intelsat IESS-308 specification. Data flow through the AHA4012B can occur in bursts at 6 MBytes per second or continuous at 1.5 MBytes per second maximum.
The AHA4012B supports several programmable parameters, including; block size, error threshold, number of check bytes and mode of operations. Shortened blocks are supported without requirement of zero padding. The data input port is used to initialize the programmable parameters and the two on-chip buffers are used to input and output data. Discontinuities in data flow may be controlled by dedicated control pins.
High operating frequency, input and output data rate flexibility, low processing latency and various programmable parameters make AHA4012B ideal for many applications including: DTV, DBS, ADSL, Satellite Communications, ISDN, High Performance Modems and networks.
This specification provides full electrical and mechanical information to help a system engineer develop a system using AHA4012B. This document contains descriptions on correction terms, pinout, functions and features, DC and AC characteristics, package and mechanical specifications, ordering information and Related Technical Publications. Software simulation of the RS code as implemented in the device is also available. Please contact AHA or its authorized sales representatives worldwide for copies of Related Technical Publications and software simulation.