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Part Number: AM79Q031

 

 

 

 

Description: The Am79Q02/021/031 Quad Subscriber Line Audio- Processing Circuit (QSLAC) devices integrate the key f...


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AM79Q031 General Description


The Am79Q02/021/031 Quad Subscriber Line Audio- Processing Circuit (QSLAC) devices integrate the key functions of analog linecards into high-performance, very-programmable, four-channel codec-filter devices.The QSLAC devices are based on the proven design of Legerity!s reliable SLAC? device families. Th advanced architecture of the QSLAC devices implements four independent channels and employs digital filters to allow software control of transmission, thus providing a cost-effective solution for the audio- processing function of programmable linecards.

Advanced submicron CMOS technology makes the Am79Q02/021/031 QSLAC devices economical, with both the functionality and the low power consumption needed in linecard designs to maximize linecard density at minimum cost. When used with four Legerity SLICs, a QSLAC device provides a complete software- configurable solution to the BORSCHT functions.

AM79Q031 Maximum Ratings

Storage Temperature 60 C TA 125 C
Ambient Operating Temperature 40 C TA 85 C
Ambient Relative Humidity 5 to 95(non-condensing)
 VCCA with respect to AGND 0.4 V to 7.0 V
 VCCA with respect toVCCD 50 m
VCCD with respect to DGND 0.4 V to 7.0 V
VIN with respect to AGND 0.4 V to (VCCA 0.4 V)
AGND with respect to DGND 0.4
Other pins with respect to DGND 0.4 V to VCCD 0.4 V
Total combined CD1 C5 current per device:Source from VCCD 40 mA
Sink into DGND 40 mA
Latch-up immunity (any pin) 100 mA

AM79Q031 Features

`Performs the functions of four codec/filters Software programmable:
`SLIC input impedanc
  Transhybrid balanc
  Transmit and receive gain
  Equalization (frequency response
  Digital I/O pin
  Programmable debouncing on one inpu
  Time slot assigne
  Programmable clock slot and PCM transmit clo edge options
`Standard microprocessor interface
`A-law, -law, or linear codin
`Single or Dual PCM ports available
  Up to 128 channels (PCLK at 8.192 MHz) per PCM port
  Optional supervision on the PCM highwa
`1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144,  6.176, or 8.192 MHz master clock derived from MCLK or PCLK
` Built-in test modes with loopback, generation, and  tone P access to PCM datao 
` Low-power, 5.0 V CMOS technology
` 5.0 V only  operation peration
` Mixed stateMixed state (analog and digital) impedance  scaling
` Performance characteristics guaranteed over a  12 dB gain range
` Real Time Data register with interrupt (open  drain or TTL output)
` Supports multiplexed SLIC inputs
` Broadcast state
` 256 kHz or 293 kHz chopper clock for Legerity  SLICs with switching regulator
` Maximum channel bandwidth for V.34 modems

AM79Q031 Connection Diagram

AM79Q031  Connection Diagram

AM79Q031 datasheet

AM79Q031
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