Features: •Pin compatible with AS7C34098
•Industrial and commercial temperature
•Organization: 262,144 words * 16 bits
•Center power and ground pins
•High speed
-10/12/15/20 ns address access time
-4/5/6/7 ns output enable access time
•Low power consumption: ACTIVE
-650 mW /max @ 10 ns
•Low power consumption: STANDBY
-28.8 mW /max CMOS
•Individual byte read/write controls
•Easy memory expansion with CE</a>, OE</a> inputs
•TTL- and CMOS-compatible, three-state I/O
•44-pin JEDEC standard packages
-400-mil SOJ
-TSOP 2
•ESD protection 2000 volts
•Latch-up current 200 mAPinout
Specifications
| Parameter |
Symbol |
Min |
Max |
Unit |
| Voltage on VCC relative to GND |
Vt1 |
-0.50 |
+5.0 |
V |
| Voltage on any pin relative to GND |
Vt2 |
0.50 |
VCC +0.50 |
V |
| Power dissipation |
PD |
|
1.5 |
W |
| Storage temperature (plastic) |
Tstg |
65 |
+150 |
°C |
| Ambient temperature with VCC applied |
Tbias |
55 |
+125 |
°C |
| DC current into outputs (low) |
IOUT |
|
±20 |
mA |
DescriptionThe AS7C34098A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words * 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 AS7C34098A ns with output enable access times (tOE) of 4/5/6/7 ns are ideal for high-performance applications. The chip enable input CE</a> permits easy memory expansion with multiple-bank memory systems.
When CE</a> is high the device enters standby mode. AS7C34098A is guaranteed not to exceed 28.8mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE</a>) and chip enable (CE</a>). Data on the input pins I/O1I/O16 is written on the rising edge of WE</a> (write cycle 1) or CE</a> (write cycle 2). To avoid bus contention, external devices of AS7C34098A should drive I/O pins only after outputs have been disabled with output enable (OE</a>) or write enable (WE</a>).
A read cycle of AS7C34098A is accomplished by asserting output enable (OE</a>) and chip enable (CE</a>), with write enable (WE</a>) high. The chip drives I/O pins with the data word referenced by the input address. When either chip of AS7C34098A enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.
AS7C34098A provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB</a> controls the lower bits, I/O1I/O8, and UB</a> controls the higher bits, I/O9I/O16.
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is for 3.3V (AS7C34098A) supply. AS7C34098A is available in the JEDEC standard 400-mL, 44-pin SOJ, TSOP 2.
AS7C34098A Data Sheet
