AS90L10208

·Two bidirectional 8-bit HyperTransport interfaces:
- Supports 200, 300, 400, 500, 600 and 800 MHz DDR (double
data rate) for peak bandwidth of 3.2GB/s per 8-bit bidirectional
HT port
- Supports dynamic frequency reprogramming
·Complies with HyperTransport 1.05 Interface Specification.
·Tunnels between the two HyperTransport interfaces.
·No protocol-induced maximum HyperTransport link length, which allows system designers to optimize speed vs. distance.
·The HT interfaces support dual-hosted chain.
·One 64-bit configurable PCI/PCI-X1.0 port:
   - 1 x 64 bit, up to 66 MHz PCI 2.2 or up to 133 MHz PCI-X 1.0b
   - 2 x 32 bit, up to 66 MHz PCI 2.2 or up to 133 MHz PCI-X 1.0b
·Complies with PCI Local Bus Specifications, Rev. 2.2
·Supports with parity and error checking features.
·Supports daisy-chaining up to 31 devices. The bandwidth is shared among the devices using a fairness algorithm.
·Built-in two-level PCI arbiter with support for up to six devices
   -Can also be configured to support an external arbiter.
·3.3 V PCI I/O with 5 V tolerant I/Os.
·Superset register compatible with the SP1011 to leverage the same software driver
·Con be configured to emulate a single or a dual SP1011 devices
·Transaction forwarding for the following commands:
   -All I/O and memory commands
   -Type 1 to Type 1 configuration commands (downstream only)
   -Type 1 to Type 0 configuration commands (downstream only)
·Evaluation board available with firmware and software drivers.
·1.8 V core, 1.2 V HT IO, 3.3 V PCI/PCI-X IO.
·JTAG port.