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Package Cooled:SOP
Part Number: AT17C128
Package Cooled: SOP
Description: The AT17C65/128/256 and AT17LV65/128/256 (AT17 Series) FPGA Configuration EEPROMS (Configurator) provide an easy-to-use...
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AT17C128
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DataSheet
General Description
AT17C128 General Description
The AT17C65/128/256 and AT17LV65/128/256 (AT17 Series) FPGA Configuration EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17 Series is pack-aged in the 8-pin DIP and the popular 20-pin PLCC and SOIC. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17 Series organization supplies enough memory to con-figure one or multiple smaller FPGAs. Using a special feature of the AT17 Series, the user can select the polarity of the reset function by programming a special EEPROM bit.
The AT17 Series can be programmed with industry standard programmers.
AT17C128 Maximum Ratings
| Operating Temperature....................... -55°C to +125°C Storage Temperature ......................... -65°C to +150°C Voltage on Any Pin with Respect to Ground ......................-0.1V to VCC +0.5V Supply Voltage (VCC) .................................-0.5V to +7.0V Maximum Soldering Temp. (10 sec. @ 1/16 in.).......260°C ESD (RZAP = 1.5K, CZAP = 100 pF).................... 2000V |
AT17C128 Features
• E2 Programmable 65,536 x 1, 131,072 x 1, and 262,144 x 1 bit Serial Memories Designed To Store Configuration Programs For Programmable Gate Arrays
• Simple Interface to SRAM FPGAs Requires Only One User I/O Pin
• Compatible With AT6000 FPGAs, ATT3000 FPGA, EPF8000 FPGAs, ORCA FPGAs, XC2000, XC3000, XC4000, XC5000 FPGAs, MPA1000
• Cascadable To Support Additional Configurations or Future Higher-density Arrays (17C128 and 17C256 only)
• Low-power CMOS EEPROM Process
• Programmable Reset Polarity
• Available In the Space-efficient Plastic DIP or Surface-mount PLCC and SOIC Packages
• In-System Programmable Via 2-Wire Bus
• Emulation of 24CXX Serial EPROMs
• Available in 3.3V ± 10% LV Version
• Simple Interface to SRAM FPGAs Requires Only One User I/O Pin
• Compatible With AT6000 FPGAs, ATT3000 FPGA, EPF8000 FPGAs, ORCA FPGAs, XC2000, XC3000, XC4000, XC5000 FPGAs, MPA1000
• Cascadable To Support Additional Configurations or Future Higher-density Arrays (17C128 and 17C256 only)
• Low-power CMOS EEPROM Process
• Programmable Reset Polarity
• Available In the Space-efficient Plastic DIP or Surface-mount PLCC and SOIC Packages
• In-System Programmable Via 2-Wire Bus
• Emulation of 24CXX Serial EPROMs
• Available in 3.3V ± 10% LV Version
AT17C128 Connection Diagram
AT17C128
PDF/DataSheet Download
- Datasheet: AT17C128
- File Size: 153431 KB
- Manufacturer: ATMEL [ATMEL Corporation]
- Click here to Download
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