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Part Number: AT17N512

 

MFG: ATMEL

 

D/C: 08+

Description: The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-touse,cost-effective config...


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AT17N512 General Description


The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-touse,cost-effective configuration memory for Field Programmable Gate Arrays. The AT17N series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP, see Table 1. The AT17N series Configurators uses a simple serial-access procedure to configure one or more FPGA devices.

The AT17N series configurators can be programmed with industry-standard programmers,Atmel's ATDH2200E Programming Kit or Atmel's ATDH2225 ISP Cable and factory programming.

AT17N512 Maximum Ratings

Operating Temperature                                                               .................................... -40 to +85
Storage Temperature                                                               ..................................... -65 to +150
Voltage on Any Pin
with Respect to Ground                                                              ..............................-0.1V to VCC +0.5V
Supply Voltage (VCC)                                                              ..........................................3.0V to +3.6V
Maximum Soldering Temp. (10 sec. @ 1/16 in.)                                                                .............260
ESD (RZAP = 1.5K, CZAP = 100 pF)                                                             ................................. 2000V

AT17N512 Features

• EE Programmable 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs)
• Available as a 3.3V (±10%) Commercial and Industrial Version
• Simple Interface to SRAM FPGAs
• Pin Compatible with Xilinx® XC17SXXXA and XC17SXXXXL PROMs
• Compatible with Xilinx Spartan®-II, Spartan-IIE and Spartan XL FPGAs in Master  Serial Mode
• Very Low-power CMOS EEPROM Process
• Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead     SOIC/VOIC Packages), 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP Packages for aSpecific Density
• Low-power Standby Mode
• High-reliability
   Endurance: Minimum 10 Write Cycles
   Data Retention: 20 Years at 85

AT17N512 Connection Diagram

AT17N512  Connection Diagram

AT17N512 datasheet

AT17N512
PDF/DataSheet Download

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