AT89C51AC3

• 80C51 Core Architecture
• 256 Bytes of On-chip RAM
• 2048 Bytes of On-chip ERAM
• 64K Bytes of On-chip Flash Memory
Data Retention: 10 Years at 85°C
Read/Write Cycle: 100K
• Boot Code Section with Independent Lock Bits
• 2K Bytes of On-chip Flash for Bootloader
• In-System Programming by On-Chip UART Boot Program and IAP Capability
• 2K Bytes of On-chip EEPROM Read/Write Cycle: 100K
• Integrated Power Monitor (POR: PFD) To Supervise Internal Power Supply
• 14-sources 4-level Interrupts
• Three 16-bit Timers/Counters
• Full Duplex UART Compatible 80C51
• High-speed Architecture
In Standard Mode:
                   40 MHz (Vcc 3V to 5.5V, both Internal and external code execution)
                   60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
In X2 mode (6 Clocks/machine cycle)
                   20 MHz (Vcc 3V to 5.5V, both Internal and external code execution)
                   30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
• Five Ports: 32 + 4 Digital I/O Lines
• Five-channel 16-bit PCA with
PWM (8-bit)
High-speed Output
Timer and Edge Capture
• Double Data Pointer
• 21-bit WatchDog Timer (7 Programmable Bits)
• A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs
• SPI Interface (PLCC52 and VPFP64 packages only)
• On-chip Emulation Logic (Enhanced Hook System)
• Power Saving Modes
Idle Mode
Power-down Mode
• Power Supply: 3 volts to 5.5 volts
• Temperature Range: Industrial (-40° to +85°C)
• Packages: VQFP44, PLCC44, VQFP64, PLCC52