AT89C51RB2-SLSUM

The AT89C51RB2-SLSUM is one member of the AT89C51RB2 series.The AT89C51RB2 is a high-performance Flash version of the 80C51 8-bit microcontrollers.It contains a 16K or 32K Bytes Flash memory block for program and data.The Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin.

Features of the AT89C51RB2-SLSUM are:1)asynchronous port reset; (2)full duplex enhanced UART; (3)dedicated baud rate generator for UART; (4)low EMI (inhibit ALE); (5)hardware watchdog timer (one-time enabled with reset-out); (6)keyboard interrupt interface on port P1; (7)SPI interface (master/slave mode); (8)8-bit clock prescaler; (9)improved X2 mode with independent selection for cpu and each peripheral; (10)ISP (in-system programming) using standard Vcc power supply; (11)boot ROM Contains low level flash programming routines and a default serial loader.In addition, the AT89C51RB2 has a Programmable Counter Array, an XRAM of 1024 Bytes, a Hardware Watchdog Timer, a Keyboard Interface, an SPI Interface, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode).

The absolute maximum ratings of the AT89C51RB2-SLSUM can be summarized as:(1)voltage on Vcc  to Vss(standard voltage):-0.5V to + 6.5V;(2)voltage on cc to Vss(low voltage):-0.5V to + 4.5V;(3)voltage on any pin to Vss:-0.5V to Vcc + 0.5V;(4)industrial temperature:-40 to 85;(5)storage temperature:-65 to 150;(6)power dissipation:1 W.Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, the user may enable the automatic address recognition feature in mode 1.In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device's address and is terminated by a valid stop bit.