Am29F100

The Am29F100 is a 1 Mbit, 5.0 Volt-only Flash memoryorganized as 131,072 bytes or 65,536 words. The Am29F100 is offered in 44-pin SO and 48-pin TSOP packages. Word-wide data appears on DQ0-DQ15;byte-wide data on DQ0-DQ7. The device is designed tobe programmed in-system with the standard system5.0 Volt VCC supply. A 12.0 volt VPP is not required forprogram or erase operations. The device can also beprogrammed or erased in standard EPROM program-mers.

The standard device offers access times of 70, 90,120, and 150 ns, allowing high-speed microproces-sors to operate without wait states. To eliminate buscontention the device has separate chip enable(CE#), write enable (WE#) and output enable(OE#)controls.

The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for thprogram and erase operations.  The device is entirely command set compatible with theJEDEC single-power-supply Flash standard. Com-mands are written to the command register using stan-dard microprocessor write timings.

Register contentsserve as input to an internal state machine that controlsthe erase and programming circuitry. Write cyclesalsointernally latch addresses and data needed for the pro-gramming and erase operations. Reading data out ofthe device is similar to reading from other Flash orEPROM devices. Device programming occurs by executing the programcommand sequence. This invokes the EmbeddedProgram algorithm-an internal algorithm that automatically times the program pulse widths and verifiesproper cell margin. vice erasure occurs by executing the erase com-mand sequence.

This invokes the Embedded Erasealgorithm-an internal algorithm that automatically pre-programs the array (if it is not already programmed) be-fore executing the erase operation. During erase, thedevice automatically times the erase pulse widths andverifies proper cell margin. host system can detect whether a program orerase operation is complete by observing the RY/BY#pin, or by reading the DQ7 (Data# Polling) and DQ6(toggle)status bits.  After a program or erase cyclehas been completed, the device is ready to read arraydata or accept another command. e Erase Suspend feature enables the system to puterase on hold for any period of time to read data from,or program data to, a sector that is not being erased.

The sector erase architecture allows memory sectorto be erased and reprogrammed without affecting thdata contents of other sectors. The device is erasewhen shipped from the factory. 

The hardware data protection measures include alow VCC detector automatically inhibits write operationsduring power transitions. The hardware sector pro-tection feature disables both program and erase oper-ations in any combination of the sectors of memory,nd is implemented using standard EPROM program-mers. The temporary sector unprotect feature allowsin-system changes to protected sectors.

The hardware RESET# pin terminates any operationin progress and resets the internal state machine toreading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus alsoreset the device, enabling the system microprocessorto read the boot-up firmware from the Flash memory.D's Flash technology combines years of Flashmemory manufacturing experience to produce thehighest levels of quality, reliability, and costeffectiveness. The device electrically erases all bitswithin a sector simultaneously via Fowler-Nordheimtunneling. The bytes are programmed one byte at atime using the EPROM programming mechanism ofhot electron injection.