Am53CF96

The Enhanced SCSI-2 Controller (ESC) was designed to support Fast SCSI-2 transfer rates of up to 10 Mbytes/s in synchronous mode and up to 7 Mbytes/s in the asynchronous mode. The ESC is downward compatible with the Am53C94/96, combining its functionality with features such as Fast SCSI, programmable Active Negation, a 24-bit transfer counter, and a part-unique ID code containing manufacturer and serial # information. AMD's proprietary features such as power-down mode for SCSI transceivers, programmable GLITCH EATER, and extended Target command set are also included for improved product performance.

The Enhanced SCSI-2 Controller (ESC) has a flexible three bus architecture. The ESC has a 16-bit DMA interface, an 8-bit host data interface and an 8-bit SCSI data interface. The ESC is designed to minimize host intervention by implementing common SCSI sequences in hardware. An on-chip state machine reduces protocol overheads by performing the required sequences in response to a single command from the host. Selection, reselection, information transfer and disconnection commands are directly supported.

The 16-byte-internal FIFO further assists in minimizing host involvement. The FIFO provides a temporary storage for all command, data, status and message bytes as they are transferred between the 16-bit host data bus and the 8-bit SCSI data bus. During DMA operations the FIFO acts as a buffer to allow greater latency in the DMA channel. This permits the DMA channel to be suspended for higher priority operations such as DRAM refresh or reception of an ISDN packet.

Parity on the DMA bus is optional. Parity can either be generated and checked or it can be simply passed through.

The Target command set for the Am53CF94/96 includes an additional command, the Access FIFO command, to allow the host or DMA controller to remove remaining FIFO data following the host's issuance of a Target abort DMA command or following an abort due to parity error. This command facilitates data recovery and
thereby minimizes the need to re-transmit data.

AMD's exclusive power-down feature can be enabled to help reduce power consumption during the chip's sleep mode. The receivers on the SCSI bus may be turned off to eliminate current that may flow because termination power (~3 V) is close to the trip point of the input buffers.

The patented GLITCH EATER Circuitry in the Enhanced SCSI-2 Controller can be programmed to filter glitches with widths up to 35 ns. It is designed to dramatically increase system reliability by detecting and removing glitches that may cause system failure. The GLITCH EATER Circuitry is implemented on the ACK and REQ lines since they are most susceptible to electrical anomalies such as reflections and voltage spikes. Such signal inconsistencies can trigger false REQ/ACK handshaking, false data transfers, addition of random data, and double clocking. AMD's GLITCH EATER Circuitry therefore maintains system performance and improves reliability. The following diagram illustrates this circuit's operation.

The Am53CF94 is also available in a 3.3 V version.