Am53C96

The High Performance SCSI Controller (HPSC) has a flexible three bus architecture. The HPSC has a 16-bit DMA interface, an 8 bit host data interface and an 8-bit SCSI data interface. The HPSC is designed to minimize host intervention by implementing common SCSI sequences in hardware. An on-chip state machine reduces protocol overheads by performing the required sequences in response to a single command from the host. Selection, reselection,  nformation transfer and disconnection commands are directly supported.
The 16-byte-internal FIFO further assists in minimizing st involvement. The FIFO provides a temporary storage or all command, data, status and message bytes as hey are transferred between the 16 bit host data bus nd the 8 bit SCSI data bus. During DMA operations the IFO acts as a buffer to allow greater latency in the DMA hannel. This permits the DMA channel to be suspended or higher priority operations such as DRAM refresh r reception of an ISDN packet.
Parity on the DMA bus is optional. Parity can either be nerated and checked or it can be simply passed hrough.
The patented GLITCH EATER Circuitry in the High Performance CSI Controller detects signal changes that  re less than or equal to 15 ns and filters them out. It is esigned to dramatically increase system performance nd reliability by detecting and filtering glitches that can ause system failure.
The GLITCH EATER Circuitry is implemented on the ACKand REQ lines only. These lines often encounter any electrical anomalies which degrade system  erformance nd reliability. The two most common are Reflections nd Voltage Spikes. Reflections are a result of igh current SCSI signals that are mismatched by stubs, ables and terminators. These reflections vary from application o application and can trigger false handshake ignals on the ACK and REQ lines if the voltage amplitude s at the TTL threshold levels. Spikes are generated y high current SCSI signals switching concurrently. On he control signals (ACK and REQ) they can trigger false ata transfers which result in loss of data, addition of andom data, double clocking and reduced system reliability. MD's GLITCH EATER Circuitry helps maintain xcellent system performance by treating the glitches. efer to the diagram on the next page.