Purchase Am79C30A/32A, In-stock Am79C30A/32A From SeekIC.
Part Number: Am79C30A/32A
Description: The Am79C30A Digital Subscriber Controller (DSC)Circuit and Am79C32A ISDN Data Controller (IDC) ...
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Am79C30A/32A
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General Description
Am79C30A/32A General Description
The Am79C30A Digital Subscriber Controller (DSC)Circuit and Am79C32A ISDN Data Controller (IDC) Circuit,shown in the Block Diagram, allow the realizationof highly-integrated Terminal Equipment for the ISDN.
The Am79C30A/32A is fully compatible with theCCITT-I-series recommendations for the S and T referencepoints, ensuring that the user of the device maydesign TEs which conform to the international standards.
The Am79C30A/32A provides a 192-Kbit/s full duplex digital path over four wires between the TE located onthe subscriber's premises and the NT or PABX linecard.
All physical layer functions and procedures areimplemented in accordance with CCITT Recommendation I.430, including framing, synchronization, maintenance,and multiple terminal contention. Bothpoint-to-point and point-to-multipoint configurations aresupported.
The Am79C30A/32A processes the ISDN basic rate bitstream, which consists of B1 (64 Kbit/s), B2 (64 Kbit/s),and D (16 Kbit/s) channels. The B channels are routed to and from different sections of the Am79C30A/32Aunder software control. The D channel is partially processedby the DSC/IDC circuit and is passed to the microprocessor for further processing.
The Main Audio Processor (MAP) uses Digital Signal Processing (DSP) to implement a high performance codec/filter function. The MAP interface supports a
loudspeaker, an earpiece, and two separate audio inputs.Programmable on-chip gain is provided to simplifyuse of low output level microphones. The user mayalter frequency response and gain of the MAP receiveand transmit paths. Tone generators are included to implementringing, call progress, and DTMF signals.
A Peripheral Port (PP) is provided to allow the B channelsto be routed off-chip for processing by other peripherals.This por t is configurable as either an
industry-standard IOM-2 port, or as a serial bus port(SBP).
The TE design process is simplified by the availabilityof certified protocol software packages, which providecomplete system solutions through OSI Layer 3.
Am79C30A/32A Features
- Level 1 Physical Layer Controller
- Supports point-to-point, short and extended
passive bus configurations
- Provides multiframe support
- Supports point-to-point, short and extended
passive bus configurations
- Provides multiframe support
Am79C30A/32A Typical Application
1. The power consumption of the DSC/IDC circuit itselfis managed by using four basic power modes which allow unused functional blocks to be disabled.
The INIT register may be programmed to selectActive Voice and Data, Active Data Only, Idle, or Power-Down mode, depending upon which DSC/IDC device resources are required at the time.
2. The power consumption of the controlling micro-processorsystem may be controlled by driving the processorclock with the DSC/IDC circuit MCLK output.
A wide range of MCLK operating frequencies may beselected, and a special Clock Speed-Up function isprovided which increases the speed of MCLK upon
the occurrence of a key event, without processor intervention.Control of MCLK frequency and Clock Speed-up is accomplished by programming the INIT
and INIT2 registers, as described later.
The INIT register may be programmed to selectActive Voice and Data, Active Data Only, Idle, or Power-Down mode, depending upon which DSC/IDC device resources are required at the time.
2. The power consumption of the controlling micro-processorsystem may be controlled by driving the processorclock with the DSC/IDC circuit MCLK output.
A wide range of MCLK operating frequencies may beselected, and a special Clock Speed-Up function isprovided which increases the speed of MCLK upon
the occurrence of a key event, without processor intervention.Control of MCLK frequency and Clock Speed-up is accomplished by programming the INIT
and INIT2 registers, as described later.
Am79C30A/32A Connection Diagram
AM7
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- Datasheet: AM7
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- ·AM70PDL127BDH85I
- SPANSION
- Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
- 938226 KB
- ·AM70PDL127BDH85IT
- SPANSION
- 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
- 940771 KB
- ·AM70PDL127CDH66IS
- SPANSION
- Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
- 867190 KB
- ·AM70PDL127CDH85IS
- SPANSION
- Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
- 867190 KB
- ·AM70PDL127CDH85IT
- SPANSION
- Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
- 867190 KB
- ·AM70PDL129BDH66I
- SPANSION
- Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)
- 938226 KB
- ·AM70PDL129BDH66IT
- SPANSION
- 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
- 940771 KB
- ·AM70PDL129BDH85IS
- SPANSION
- 2 x 64 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-Only Page Mode Flash Memory Data Storage 128 Megabit (8 M x 16-Bit) CMOS
- 940771 KB
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