Am79C965A

The PCnet-32 single-chip 32-bit Ethernet controller is a highly integrated Ethernet system solution designed to address high-performance system application requirements. It is a flexible bus-mastering device that can be used in any networking application, including networkready PCs, printers, fax modems, and bridge/router designs. The bus-master architecture provides high data throughput in the system and low CPU and bus utilization. The PCnet-32 controller is fabricated with AMD's advanced low-power CMOS process to provide low operating and standby current for power-sensitive applications.  The PCnet-32 controller is a complete Ethernet node integrated into a single VLSI device. It contains a bus interface unit, a DMA buffer management unit, an ISO 8802-3 (IEEE/ANSI 802.3)-defined media access control (MAC) function, individual 136-byte transmit and 128-byte receive FIFOs, an ISO 8802-3  IEEE/ANSI 802.3)-defined attachment unit interface (AUI) and twisted-pair transceiver medium attachment unit  0BASE-T MAU), and a microwire EEPROM  nterface.  The PCnet-32 controller is also register-compatible with the LANCE (Am7990) Ethernet controller, the CLANCE (Am79C90) Ethernet controller, the ILACC Am79C900) Ethernet controller, and all Ethernet controllers in the PCnet family, including the PCnet-ISA controller (Am79C960), the PCnet-ISA+ controller Am79C961), PCnet-ISA II  Am79C961A), and the PCnet-PCI II controller (Am79C970A). The buffer  anagement uni t suppor ts the LANCE, ILACC Am79C900), and PCnet descriptor software models.  The PCnet-32 controller is software-compatible with Novell NE2100 and NE1500 Ethernet adapter card architectures. In addition, a Sleep function has been incorporated to provide low standby current, which is essential for notebooks and Green PCs.

The 32-bit demultiplexed bus interface unit provides a direct interface to the VESA VL-Bus and 486 series icroprocessors, simplifying the design of an Ethernet node in a PC system. With its built-in support for both little and big endian byte alignment, this controller also addresses proprietary non-PC applications.

Key PCnet-32 configuration parameters, including the unique IEEE physical address, can be read from an external non-volatile memory (serial EEPROM) immediately following system reset. In addition, the I/O location at which the internal registers are accessed may be stored in the EEPROM, allowing the software model of the device to be located appropriately in system I/O space during system initialization.

The controller has the capability to select automatically either the AUI port or the twisted-pair transceiver. Only one interface is active at any one time. The individual transmit and receive FIFOs reduce system overhead, providing sufficient latency during frame transmission and reception, and minimizing intervention during normal network error recovery. The integrated Manchester encoder/decoder (MENDEC) eliminates the need for an external serial interface adapter (SIA) in the node system. The built-in general purpose serial interface (GPSI) allows the MENDEC to be  ypassed. In addition, the device provides programmable on-chip LED drivers for transmit, receive, collision, receive polarity, link integrity, or jabber status. The PCnet-32 controller also provides an external address detection interface (EADI) to allow external hardware address filtering in inter-networking applications.