Features: • High Voltage Type (20V Rating)
• Medium Speed Operation tPHL = tPLH = 60ns (typ.) at CL = 50pF, VDD = 10V
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
• Maximum Input Current of 1a at 18V Over Full Package- Temperature Range;
100nA at 18V and 25oC
• Noise Margin (Over Full Package Temperature Range):
1V at VDD = 5V
2V at VDD = 10V
2.5V at VDD = 15V
Application• And/Or Select Gating
• Shift-Right/Shift-Left Registers
• True/Complement Selection
• AND/OR/Exclusive-OR Selection
Pinout
SpecificationsDC Supply Voltage Range, (VDD) ... -0.5V to +20V (Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs ...........................................................0.5V to VDD +0.5V
DC Input Current, Any One Input ............................................................................10mA
Operating Temperature Range...................... -55 to +125 Package Types D, F, K, H
Storage Temperature Range (TSTG) .....................................................-65 to +150
Lead Temperature (During Soldering) ................................................................ +265
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum
DescriptionCD4019BMS types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single 2-input OR gate. Selection is accomplished by control bits Ka and Kb. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.
The CD4019BMS is supplied in these 16-lead outline packages:
Braze Seal DIP H4T
Frit Seal DIP H1E
Ceramic Flatpack H3X
CD4019BMS Data Sheet
