CD4027BM

Maximum Operating Temperature : + 125 C
Mounting Style : SMD/SMT
Number of Circuits : 2
Input Type : Single-Ended
Packaging : Tube
Polarity : Inverting/Non-Inverting
Output Type : Differential
Package / Case : SOIC-16
Propagation Delay Time : 300 ns
High Level Output Current : - 4.2 mA
Low Level Output Current : 4.2 mA
Supply Voltage - Max : 18 V
Logic Type : J-K Type Flip-Flop
Logic Family : 40


Features:

Wide supply voltage range 3.0V to 15V
High noise immunity 0.45 VDD (typ.)
Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS
Low power 50 nW (typ.)
Medium speed operation+ 12 MHz (typ.)
                                with 10V supply


Pinout




Specifications

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
DC Supply Voltage (VDD)  . . . . . . . . . . . . . .b0.5 VDC to a18 VDC
Input Voltage (VIN) . . . . . . . . . .  . . .. . . . b0.5V to VDD a0.5 VDC
Storage Temperature Range (TS)  . . . . . . . . . . .b65ßC to a150ßC
Power Dissipation (PD)
 Dual-In-Line  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .700 mW
 Small Outline  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500 mW
Lead Temperature (TL)
 (Soldering, 10 seconds)  . . . . . . . . . . . . . . . . . . . . . . . . . . .260ßC


Description

CD4027BM dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and Pchannel enhancement mode transistors. CD4027BM Each flip-flop has independent J, K, set, reset, and clock inputs and buffered
Q and Q outputs. CD4027BM flip-flops are edge sensitive to the clock input and change state on the positive-going transition of the clock pulses. Set or reset is independent of the clock and is accomplished by a high level on the respective input. All inputs are protected against damage due to static discharge by diode clamps to VDD and VSS.