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CD4072BMS

Features: • High-Voltage Types (20V Rating)• CD4071BMS Quad 2-Input OR Gate• CD4072BMS Dual 4-Input OR Gate• CD4075BMS Triple 3-Input OR Gate• Medium Speed Operation: - tPHL, tPLH = 60ns (typ) at 10V• 100% Tested for Quiescent Current at 20V• Maximum Input...

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SeekIC No. : 004311336 Detail

CD4072BMS: Features: • High-Voltage Types (20V Rating)• CD4071BMS Quad 2-Input OR Gate• CD4072BMS Dual 4-Input OR Gate• CD4075BMS Triple 3-Input OR Gate• Medium Speed Operation: -...

CD4072BMS Data Sheet

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Part Number:
CD4072BMS
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• High-Voltage Types (20V Rating)
• CD4071BMS Quad 2-Input OR Gate
• CD4072BMS Dual 4-Input OR Gate
• CD4075BMS Triple 3-Input OR Gate
• Medium Speed Operation:
  - tPHL, tPLH = 60ns (typ) at 10V
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-age Temperature Range; 100nA at 18V and +25oC
• Standardized Symmetrical Output Characteristics
• Noise Margin (Over Full Package Temperature Range):
  - 1V at VDD = 5V
  - 2V at VDD = 10V
  - 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"


Specifications

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . . -0.5V to +20V
   (Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs  . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input  . . . . . . . . . . . . . . . . . . . . . ±10mA
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
   Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering)  . . . . . . . . . . . . . . . . . +265oC
   At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum


Description

CD4071BMS, CD4072BMS and CD4075BMS OR gates pro-vide the system designer with direct implementation of the positive-logic OR function and upplement the existing fam-ily of CMOS gates.

The CD4071BMS, CD4072BMS and CD4075BMS are supplied in these 14 lead outline packages:
Braze Seal DIP                     *H4H †H4Q
Frit Seal DIP                                     H1B
Ceramic Flatpack                            H3W
*CD4071, CD4072           †CD4075 Only




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