CD74AC251

Features:

• Buffered Inputs
• Typical Propagation Delay
  - 6ns at V_CC = 5V, T_A = 25, C_L = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
• SCR-Latchup-Resistant CMOS Process and Circuit Design
• Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
  - Fanout to 15 FAST™ ICs
  - Drives 50W Transmission Lines


Pinout




Specifications

DC Supply Voltage, V_CC . . . . . . . . . . . . . . . . . . . . . . .  . -0.5V to 6V
DC Input Diode Current, I_IK
For V_I < -0.5V or V_I > V_CC + 0.5V . . . . . . . . . . . . . . .  . . . . .±20mA
DC Output Diode Current, I_OK
For V_O < -0.5V or V_O > V_CC + 0.5V . . . . . . . . . . . . . . . . . .. .±50mA
DC Output Source or Sink Current per Output Pin, I_O
For V_O > -0.5V or V_O < V_CC + 0.5V . . . . . . . . . . . . . . . .  .  . .±50mA
DC V_CC or Ground Current, I_CC or I_GND (Note 3) . . . . . .  . .±100mA


Description

The CD74AC251 and CD74ACT251 8-input multiplexers that utilize the Harris Advanced CMOS Logic technology. This CD74AC251 multiplexer features both true (Y) and complement (Y) outputs as well as an Output Enable (OE) input. The OEmust be at a LOW logic level to enable this device. When the OE input is HIGH, both outputs are in the high-impedance state. When enabled, address information on the data select inputs determines which data input is routed to the Y and Y outputs.