CD74AC283

Features: • Buffered Inputs• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015• SCR-Latchup-Resistant CMOS Process and Circuit Design• Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption• Balanced Propagation Delays• AC Types Feature...

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CD74AC283 Picture
SeekIC No. : 004311893 Detail

CD74AC283: Features: • Buffered Inputs• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015• SCR-Latchup-Resistant CMOS Process and Circuit Design• Speed of Bipolar FAST™/AS/S wit...

floor Price/Ceiling Price

Part Number:
CD74AC283
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/24

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Product Details

Description



Features:

• Buffered Inputs
• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
• SCR-Latchup-Resistant CMOS Process and Circuit Design
• Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
  - Fanout to 15 FAST™ ICs
  - Drives 50W Transmission Lines



Pinout

  Connection Diagram


Specifications

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . .  . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . .  . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . .. .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .  .  . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . .  . .±100mA
 


Description

The 'AC283 and 'ACT283 4-bit binary adders with fast carry that utilize Advanced CMOS Logic technology. These devices add two 4-bit binary numbers and generate a carryout bit if the sum exceeds 15.

Because of the symmetry of the add function,CD74AC283 can be used with either all active-HIGH operands (positive logic) or with all active-LOW operands (negative logic). When using positive logic, the carry-in input must be tied LOW if there is no carry-in.


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