CD74ACT161 General Description
CD74ACT161 Maximum Ratings
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.5 V to 6 V
Input clamp current, IIK (VI < 0 V or VI > VCC) (see Note 2) . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 V or VO > VCC) (see Note 2) . . . . . ±50 mA
Continuous output current, IO (VO > 0 V or VO < VCC) . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . .. . . . ±100 mA
Package thermal impedance, JA (see Note 3): E package . . . . . . . .. . 67/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . 65 to 150
CD74ACT161 Features
·Inputs Are TTL-Voltage Compatible
·Internal Look-Ahead for Fast Counting
·Carry Output for n-Bit Cascading
·Synchronous Counting
·Synchronously Programmable
·SCR-Latchup-Resistant CMOS Process and Circuit Design
·Exceeds 2 kV ESD Protection per MIL-STD-883, Method 3015
·Package Options Include Plastic Small-Outline (M) Standard Plastic (E) and Ceramic (F) DIPs
CD74ACT161 Connection Diagram
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