CD74ACT175

Features:

• Buffered Inputs
• Typical Propagation Delay
  - 6.4ns at V_CC = 5V, T_A = 25, C_L = 50pF
• Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
• SCR-Latchup-Resistant CMOS Process and Circuit Design
• Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
  - Fanout to 15 FAST™ ICs
  - Drives 50W Transmission Lines

Pinout




Specifications

DC Supply Voltage, V_CC . . . . . . . . . . . . . . . . . . . . . . .  . -0.5V to 6V
DC Input Diode Current, I_IK
For V_I < -0.5V or V_I > V_CC + 0.5V . . . . . . . . . . . . . . .  . . . . .±20mA
DC Output Diode Current, I_OK
For V_O < -0.5V or V_O > V_CC + 0.5V . . . . . . . . . . . . . . . . . .. .±50mA
DC Output Source or Sink Current per Output Pin, I_O
For V_O > -0.5V or V_O < V_CC + 0.5V . . . . . . . . . . . . . . . .  .  . .±50mA
DC V_CC or Ground Current, I_CC or I_GND (Note 3) . . . . . .  . .±100mA 


Description

The CD74AC175 and CD74ACT175 are quad D flip-flops with reset that utilize the Harris Advanced CMOS Logic technology. CD74ACT175 Information at the D input is transferred to the Q and Q outputs on the positive-going edge of the clock pulse. All four flip-flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a LOW logic level independent of the clock.