CD74FCT273

Features: BiCMOS Technology With Low Quiescent PowerBuffered InputsDirect Clear Input48-mA Output Sink CurrentOutput Voltage Swing Limited to 3.7 VControlled Output Edge RatesInput/Output Isolation From VCCSCR Latch-Up-Resistant BiCMOS Process and Circuit DesignApplications Include: Buffer/Storag...

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CD74FCT273 Picture
SeekIC No. : 004311926 Detail

CD74FCT273: Features: BiCMOS Technology With Low Quiescent PowerBuffered InputsDirect Clear Input48-mA Output Sink CurrentOutput Voltage Swing Limited to 3.7 VControlled Output Edge RatesInput/Output Isolation ...

floor Price/Ceiling Price

Part Number:
CD74FCT273
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/26

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Product Details

Description



Features:

 BiCMOS Technology With Low Quiescent Power
 Buffered Inputs
 Direct Clear Input
 48-mA Output Sink Current
 Output Voltage Swing Limited to 3.7 V
 Controlled Output Edge Rates
 Input/Output Isolation From VCC
 SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
 Applications Include:
   Buffer/Storage Registers
   Shift Registers
   Pattern Generators
Package Options Include Plastic Small-Outline (M) Package and Standard Plastic (E) DIP



Pinout

  Connection Diagram


Specifications

DC supply voltage range, VCC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 6 V
DC input clamp current, IIK (VI < 0.5 V)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mA
DC output clamp current, IOK (VO < 0.5 V)  . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .50 mA
DC output sink current per output pin, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .70 mA
DC output source current per output pin, IOH  . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . .30 mA
Continuous current through VCC, (ICC)  . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  140 mA
Continuous current through GND  . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. .400 mA
Package thermal impedance, JA (see Note 1)  EN package  . .. . . . . . . . . . . . . . . . . .69°C/W
                                                                          M package . . . . . . . . . . . . . . . . . . . . 58°C/W
Storage temperature range, Tstg  . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .. . . 65°C to 150°C
 


Description

The CD74FCT273 is a positive-edge-triggered, D-type flip-flop with a direct clear (CLR) input. CD74FCT273 uses a small-geometry BiCMOS technology. The CD74FCT273 output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The CD74FCT273 output configuration also enhances switching speed and is capable of sinking 48 mA.

CD74FCT273 Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. CD74FCT273 Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. All eight flip-flops are controlled by a common clock (CLK) and a common reset (CLR). The outputs are placed in a low state when CLR is taken low, independent of the CLK.

The CD74FCT273 is characterized for operation from 0°C to 70°C.




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