CD74FCT573AT

• Buffered Inputs
• Typical Propagation Delay: 3.9ns at V_CC = 5V, T_A = 25, C_L = 50pF (CD74FCT573AT)
• SCR Latchup Resistant BiCMOS Process and Circuit Design
• FCTXXX Types
     Speed of Bipolar FAST™/AS/S
• FCTXXXAT Types
    30% Faster than FAST™/AS/S with Significantly Reduced Power Consumption
• 48mA Output Sink Current
• Output Voltage Swing Limited to 3.7V at V_CC = 5V
• Controlled Output Edge Rates
• Input/Output Isolation to V_CC
• BiCMOS Technology with Low Quiescent Power

DC Supply Voltage (V_CC) . . . . . . . . . . . . . . . . . . . . . . .. -0.5V to 6V
DC Input Diode Current, I_IK (For V_I < -0.5V) . . . . . . . . . . .  . -20mA
DC Output Diode Current, I_OK (for V_O < -0.5V) . . . . . . . . . .  -50mA
DC Output Sink Current per Output Pin, I_O . . . . . . . . . . . . . ..70mA
DC Output Source Current per Output Pin, I_O . . . . . . . . . . .. -30mA
DC VCC Current (I_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140mA
DC Ground Current (I_GND). . . . . . . . . . . . . . . . . . . . . . . . . . .400mA

The CD74FCT573 and CD74FCT573AT octal transparent latches use a small geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output HIGH level to two diode drops below V_CC. This resultant lowering of output swing (0V to 3.7V) reduces power bus ringing (a source of EMI) and minimizes V_CC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 milliamperes.

The CD74FCT573 and CD74FCT573AT outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enable (OE) controls the three-state outputs. When the Output Enable (OE) is HIGH, the outputs are in the high impedance state. The latch operation is independent of the state of the Output Enable.