CD74FCT646

The CD74FCT646 three-state octal bus transceiver/register uses a small geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output HIGH level to two diode drops below VCC. CD74FCT646 resultant lowering of output swing (0V to 3.7V) reduces power bus ringing (a source of EMI) and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The CD74FCT646 output configuration also enhances switching speed and is capable of sinking 64 milliamperes.

CD74FCT646 is a bus transceiver with D-Type flip-flops which act as internal storage registers on the LOW to HIGH transi- tion of either CAB or CBA clock inputs. CD74FCT646 Output Enable (OE) and Direction (DIR) inputs control the transceiver functions. Data present at the high impedance output can be stored in either register or both but only one of the two buses can be enabled as outputs at any one time. The Select controls (SAB and SBA) can multiplex stored and ransparent (real time) data. The Direction control determines which data bus will receive data when the Output Enable (OE) is LOW. In the high impedance mode (Output Enable HIGH), A data can be stored in one register and B data can be stored in the other register. The clocks are not gated with the Direction (DIR) and Output Enable (OE) terminals; data at the A or B termi- nals can be clocked into the storage flip-flops at any time.