CDCP1803-EP

The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0] with minimum skew for clock distribution. The CDCP1803 is specifically designed for driving 50- Ω transmission lines.

Features of the CDCP1803-EP are:(1)Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs; (2)Programmable Output Divider for Two LVPEC Outputs; (3)Low-Output Skew 15 ps (Typical); (4)V CC Range 3 V 3.6 V; (5)Signaling Rate Up to 800-MHz LVPECL; (6)Differential Input Stage for Wide Common-Mode Range; (7)Provides VBB Bias Voltage Output for Single-Ended Input Signals; (8)Receiver Input Threshold ± 75 mV; (9)24-Terminal QFN Package (4 mm * 4 mm); (10)Accepts Any Differential Signaling: LVDS, HSTL, CML, VML, SSTL-2, and Single-Ended: LVTTL/LVCMOS.

The absolute maximum ratings of the CDCP1803-EP can be summarized as:(1)Supply voltage 0.3 V to 3.8 V; (2)Input voltage 0.2 V to (V DD + 0.2 V); (3)Output voltage 0.2 V to (V DD + 0.2 V); (4)Differential short-circuit current, Yn, Yn , I OSD Continuous; (5)Electrostatic discharge (HBM 1.5 k , 100 pF), ESD > 2000 V; (6)Moisture level 24-terminal QFN package (solder reflow temperature of 235 ° C) MSL 2; (7)Storage temperature 65 ° C to 150 ° C; (8)Maximum junction temperature 150 ° C.

If you want to know more CDCP1803-EP information such as the electrical characteristics ,please download the datasheet in www.seekdatasheet.com .