CDP1823

Features:

• Fast Access Time
- VDD = 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450ns
- VDD = 10V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns
• Common Data Inputs and Outputs
• Multiple Chip Select Inputs to Simplify Memory System Expansion


Pinout




Specifications

DC Supply Voltage Range, (V_DD) (All Voltages Referenced to V_SS Terminal) CDP1823 . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1823C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . .  . . . . . . .  . . . . . . .  . . . . . . .  . . . . . . .  . . . . . . .  . . . .-0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . .  . . . . .  . . . . .  . . . . .  . . . . .  . . . . .  . . . . .  . . . . .  . . . . .  . . . .-0.5V to V_DD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range (T_A) Package Type D . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC


Description

The CDP1823 and CDP1823C are 128-word by 8-bit CMOS SOS static random-access memories. These memories are compatible with general-purpose microprocessors. The two memories are functionally identical. They differ in that the CDP1823 has a recommended operating voltage range of 4V to 10.5V, and the CDP1823C has a recommended operating voltage range of 4V to 6.5V.
The CDP1823 memory has 8 common data input and data output terminals for direct connection to a bidirectional data bus and is operated from a single voltage supply. Five chipselect inputs are provided to simplify memory-system expansion. In order to enable the CDP1823, the chip-select inputs CS2, CS3 and CS5 require a low input signal, and the chipselect inputs CS1 and CS4 require a high input signal.
CDP1823 MRD signal enables all 8 output drivers when in the low state and should be in a high state during a write cycle. After valid data appear at the output, the address inputs may be changed immediately. Output data will be valid until either the MRD signal goes high, the device is deselected, or tAA (access time) after address changes.