Features: • 70MSPS
• Wide dynamic range
SFDR: 74dBc
SFDR w/dither: 85dBFS
SNR: 67dB
• IF sampling capability
• Input bandwidth = 0-300MHz
• Low power dissipation: 640mW
• Very small package: 48-pin TSSOP
• Single +5V supply
• Data valid clock output
• Programmable output levels: 3.3V or 2.5VApplication• Cellular base-stations
• Digital communications
• Infrared/CCD imaging
• IF sampling
• Electro-optics
• Instrumentation
• Medical imaging
• High definition videoPinout
Specificationspositive supply voltage (VCC) -...........0.5V to +6V
differential voltage between any two grounds ....<100mV
analog input voltage range............ GND to VCC
digital input voltage range........... -0.5V to +VCC
output short circuit duration (one-pin to ground)... infinite
junction temperature ..................175
storage temperature range ........ ..-65 to 150
lead solder duration (+300) ........ ..... 10sec
Note: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device reliability.
| Temperature Min |
-40 deg C |
| Temperature Max |
85 deg C |
| Resolution |
12 bits |
| INL (+/-) |
1.5 LSB |
| ENOB |
10.5 bits |
| SINAD |
65.5 dB |
| SNR |
67 dB |
| THD dB |
-71 dB |
| SFDR |
74 dB |
| PowerWise |
No |
| View Using Catalog |
DescriptionThe CLC5957 is a monolithic 12-bit, 70MSPS analog-to-digital converter. The device has been optimized for use in IF-sampled digital receivers and other applications where high resolution, high sampling rate, wide dynamic range, low power dissipation, and compact size are required. The CLC5957 features differential analog inputs, low jitter differential universal clock inputs, a low distortion track-and-hold with 0-300MHz input bandwidth, a bandgap voltage reference, data valid clock output, TTL compatible CMOS (3.3V or 2.5V) programmable output logic, and a proprietary 12-bit multi-stage quantizer. The CLC5957 is fabricated on the ABIC-V 0.8 micron BiCMOS process.
The CLC5957 features a 74dBc spurious free dynamic range (SFDR) and a 67dB signal to noise ratio (SNR). The wideband track-and-hold allows sampling of IF signals to greater than 250MHz. The part produces two-tone, dithered, SFDR of 83dBFS at 75MHz input frequency. The differential analog input provides excellent common mode rejection, while the differential universal clock inputs minimize jitter. The 48-pin TSSOP package provides an extremely small footprint for applications where space is a critical consideration. The CLC5957 operates from a single +5V power supply. Operation over the industrial temperature range of -40°C to +85°C is guaranteed. National Semiconductor tests each part to verify compliance with the guaranteed specifications.
Reliability Metrics
| Part Number |
Process |
EFR Reject |
EFR Sample Size |
PPM |
LTA Rejects |
LTA Device Hours |
FITS |
MTTF (Hours) |
| CLC5957MTD |
ABIC |
0 |
15413 |
0 |
0 |
2558000 |
2 |
725839484 |
| CLC5957MTDX |
ABIC |
0 |
15413 |
0 |
0 |
2558000 |
2 |
725839484 |
Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.For more information on Reliability Metrics, please click here.
Design Tools
| Title |
Size in Kbytes |
Date |
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| Evaluation Systems |
32 Kbytes |
2-Jun-2008 |
View |
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| Eval Board Users' Guide |
992 Kbytes |
19-Aug-1999 |
View Online |
Download |
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CLC5957 Data Sheet
