CMOS-8LCX

The CMOS-8LCX has the following features including Supports Crosscheck on-chip testability circuitry;Internal gate delays of 131 ps (F/O=1;L=0 mm);Channelless, 0.50 pm CMOS architecture;Power (typ.)=1.24 (3.3V)=0.80 (3.0V);Process technology designed for 3V operation;I/Os interface directly to 5V logic;48mA GTL I/O buffers are in development;Phase Locked Loop (PLL) for chip-to-chip clock synchronization in development;Automated generation of clock network for skew minimization;High pad to gate ratio optimizes silicon usage.

NEC's 3-volt CMOS-8LCX family consists of ultra-high performance, sub-micron gate arrays, targeted for applications requiring extensive integration and high speeds. The device processing includes a true 3-volt,0.5-micron (drawn) silicon-gate CMOS technology and three-layer metalization. This technology features channelless (sea-of-gates) architecture with an internal gate delay of 131 ps (F/O=1;L=0 mm).The PD658xx series of 3-volt Crosscheck.-supported devices consists of 10 masters, offered in densities of 10K gates to 486K gates. Usable gates range from 32K gates to 389K gates. These gate arrays are ideal for use in engineering workstations, high-end PCs, mainframes and LAN products, where extensive integration and high speed are primary design goals. CMOS-8LCX gate arrays are also well-suited for all battery-operated applications where high performance and low power consumption are critical; and feasible only with a truly optimized 3-volt CMOS process.

CMOS-SLCX gate arrays support automatic test generation through Crosscheck Technology's testability structures. This results in high fault coverage ATPT of synchronous and asynchronous designs CMOS-8LCX with no netlist modifications and without designer involvement.As a general rule, the round-trip delay of the line should not exceed the rise or fall time of the driving signal.Transmission lines that are longer than those determined by this rule can degrade system performance due to reflections and ringing.  One benefit of slew-rate output buffers is that longer interconnections on a PC board and routing flexibility are possible.ASIC designers, therefore, can slow down the output edge-rate by using a slew-rate output buffer and thus accommodate longer transmission lines on PC boards.