CX5000

The 0.18um CX5000 is an ASIC that utilizes the combination of an advanced metal programmable gate array and optimized EDA system to implement high performance ASIC designs while reducing application tooling costs and design turnaround time. ASIC designers using the CX5000 are able to meet or exceed their design schedules and budgets without compromising technical objectives.

The CX5000 comprises a family of pre-configured platform masterslices that contain varying amounts of general-purpose logic, fast memory, advanced I/Os, clock synthesis and phase management macrocells. When combined with a mix of popular thirdparty tools and custom designed point EDA solutions, the CX5000 provides not just gate array hardware, but also a complete ASIC Platform from which to develop today's advanced SoC ASICs.

Manufactured in UMC's 0.18um, 6-layer metal CMOS process, the CX5000 combines the reliability and quality of an industry-leading silicon foundry, with the high performance, low power consumption and fast design turnaround time of ChipX Structured ASIC technology. The CX5000 family is very applicable to cost reduction projects, replacing expensive FPGA devices with low-cost metal programmable technology. The CX5000 is the first viable "standard cell alternative" ASIC technology, developed in response to the growing need for cost-effective ASIC implementation capability.

The CX5000 Structured ASIC technology uses just two of the six available metal layers to program the logic, memory, I/O and clocking of an ASIC design and so eliminates the large costs of the remaining "fixed" masks. Wafers are manufactured up to Metal 4, where they are held pending completion of the customer application. Completed chips can be delivered to the customer less than three weeks after signoff of the finished design.

ChipX Structured ASIC technology is very similar in concept to FPGA, which makes it easy to use and familiar to most ASIC and system designers. Using metal interconnect segments rather than SRAM cells to program the ASIC, CX5000 technology reduces the area of the chip by between 5x and 10x over the equivalent FPGA and brings performance up to 90% of standard cell design speeds.