CY2309

ApplicationThe CY2305 and CY2309 are an excellent clocking solution for a system that requires more PCI clocks than the currently popular clock chips provide. The CY2305 comes in a tiny 150 mil 8-pin SOIC package and the CY2309 comes in a small 150-mil 16-pin SOIC package. The CY2305 and CY2309 ar...

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SeekIC No. : 004319150 Detail

CY2309: ApplicationThe CY2305 and CY2309 are an excellent clocking solution for a system that requires more PCI clocks than the currently popular clock chips provide. The CY2305 comes in a tiny 150 mil 8-pi...

floor Price/Ceiling Price

Part Number:
CY2309
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/19

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Product Details

Description



Application

The CY2305 and CY2309 are an excellent clocking solution for a system that requires more PCI clocks than the currently popular clock chips provide. The CY2305 comes in a tiny 150 mil 8-pin SOIC package and the CY2309 comes in a small 150-mil 16-pin SOIC package. The CY2305 and CY2309 are priced very aggressively for the high volume PC market. There are two solutions for implementing a PCI zero delay buffer with the Cypress zero delay buffers: a 5 device/ slot and a 9 device/slot buffer. The 5 Device/Slot Solution:
• PCI/Slot 1 (CLKOUT) must always be loaded.
• If PCI Slots represent different loads, they will have earlier or later clocks (See Lead or Lag Adjustments section of "Special Features of Cypress Zero Delay Buffers".
The CY2305 is an excellent clocking solution for a system using 1 SDRAM DIMM. The CY2305 comes in a very small 150-mil 8-pin SOIC package and is priced very aggressively for the high volume PC market. There are two solutions for implementing 1 SDRAM DIMM support with the CY2305: the first is the adjustable delay solution, and the second is the self adjusting delay solution.
The Adjustable Delay Solution:
• Cload must be equal to SDRAM module loading for zero delay.
• To make the SDRAM inputs lead or lag the reference input see the Lead or Lag Adjustments section of "Special Features of the Cypress Zero Delay Buffers".



Pinout

  Connection Diagram


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