CY28352

This PLL clock buffer is designed for 2.5-V_DD and 2.5-AV_DD operation and differential output levels.

CY28352 is a zero delay buffer that distributes a clock input CLKIN to six differential pairs of clock outputs (CLKT[0:5], CLKC[0:5]) and one feedback clock output FBOUT. The clock outputs are controlled by the input clock CLKIN and the feedback clock FBIN.

The two-line serial bus can set each output clock pair (CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.

The PLL in CY28352 uses the input clock CLKIN and the feedback clock FBIN to provide high-performance, low-skew, lowjitter output differential clocks.