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CY2DP814

Features: Low voltage operationVDD = 3.3V1:4 fanoutSingle-input configurable for LVDS, LVPECL, or LVTTLFour differential pairs of LVPECL outputsDrives 50-ohm loadLow input capacitanceLow output skewLow propagation delay -Typical (tpd < 4 ns)Industrial versions availableAvailable packages includ...

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SeekIC No. : 004319291 Detail

CY2DP814: Features: Low voltage operationVDD = 3.3V1:4 fanoutSingle-input configurable for LVDS, LVPECL, or LVTTLFour differential pairs of LVPECL outputsDrives 50-ohm loadLow input capacitanceLow output skew...

CY2DP814 Data Sheet

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Part Number:
CY2DP814
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

Low voltage operation
VDD = 3.3V
1:4 fanout
Single-input configurable for LVDS, LVPECL, or LVTTL
Four differential pairs of LVPECL outputs
Drives 50-ohm load
Low input capacitance
Low output skew
Low propagation delay
    -Typical (tpd < 4 ns)
Industrial versions available
Available packages include TSSOP, SOIC


Pinout

Connection Diagram


Specifications

Storage Temperature: ........................................................................65°C to +150°C
Ambient Temperature:...........................................................................40°C to +85°C
Supply Voltage to Ground Potential (Inputs and VCC only)....................... 0.3V to 4.6V
Supply Voltage to Ground Potential (Outputs only) ........................0.3V to VDD + 0.3V
DC Input Voltage .............................................................................0.3V to VDD + 0.3V
DC Output Voltage.......................................................................... 0.3V to VDD + 0.9V
Power Dissipation.................................................................................................. 0.75W


Description

The Cypress CY2 series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industry's fastest logic.

The Cypress CY2DP814 fanout buffer features a single LVDSor a single LVPECL-compatible input and four LVPECL output pairs.

Designed for data communications clock management applications, the fanout from a single input reduces loading on the input clock.

The CY2DP814 is ideal for both level translations from single-ended to LVPECL and/or for the distribution of LVDS-based clock signals. The Cypress CY2DP814 has configurable input between logic families. The input can be selectable for an LVPECL/LVTTL or LVDS signal, while the output drivers support LVPECL capable of driving 50-ohm lines.




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