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CY2HH8110

Features: • DC to 150-MHz operation• 1.5V power supply• One single-ended HSTL input• Ten single-ended Class II HSTL outputs• Less than 1.9% Duty Cycle distortion• Balanced 16-mA output drive• Output Enable/Disable• Low output-output skew• Opera...

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SeekIC No. : 004319294 Detail

CY2HH8110: Features: • DC to 150-MHz operation• 1.5V power supply• One single-ended HSTL input• Ten single-ended Class II HSTL outputs• Less than 1.9% Duty Cycle distortion•...

CY2HH8110 Data Sheet

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Part Number:
CY2HH8110
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• DC to 150-MHz operation
• 1.5V power supply
• One single-ended HSTL input
• Ten single-ended Class II HSTL outputs
• Less than 1.9% Duty Cycle distortion
• Balanced 16-mA output drive
• Output Enable/Disable
• Low output-output skew
• Operating temperature range: 0°C to +85°C
• 32-pin TQFP package


Pinout

Connection Diagram


Specifications

Parameter Description Condition
Min.
Max.
Unit
VDD DC Supply Voltage  
3.3
V
VDD DC Operating Voltage Functional
2.625
V
VIN DC Input Voltage Relative to VSS, with or VDD applied
VDD + 0.5
V
VOUT DC Output Voltage Relative to VSS
VDD + 0.5
V
VTT Output termination Voltage  
VDD ÷ 2
V
LU Latch Up Immunity Functional
200
mA
RPS Power Supply Ripple Ripple Frequency < 100 kHz
150
mVp-p
TS Temperature, Storage Non-functional
65
+150
°C
TA Temperature, Operating Ambient Functional
0
+85
°C
TJ Temperature, Junction Functional
+150
°C
ØJC Dissipation, Junction to Case Functional
42
°C/W
ØJA Dissipation, Junction to Ambient Functional
105
°C/W
ESDH ESD Protection (Human Body Model)   1600
V
FIT Failure in Time Manufacturing test
10
ppm
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.


Description

The CY2HH8110 is a low-voltage HSTL fanout buffer designed for data communications, clock management, and specialty memory applications.

The class II HSTL outputs are balanced Push-Pull in design capable of delivering 16 mA into 10 pF load. This class allows both source series termination and symmetrically double parallel termination.

The CY2HH8110 low-output duty cycle distortion makes it suitable for Double Data Rate (DDR) applications.




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