CY3115

CY3115 Warp2 is a state-of-the-art HDL compiler for designing with Cypress's Complex Programmable Logic Devices (CPLDs). Warp2 utilizes a subset of IEEE 1364 Verilog as its Hardware Description Language (HDL) for design entry. Another design entry method supported by Warp2 is through Aldec's Active-HDL™FSM graphical Finite State Machine Editor (PC only). Warp2 accepts Verilog, synthesizes and optimizes the entered design, and outputs a JEDEC map for the desired PLD or CPLD (see Figure 1). For simulation, Warp2 provides a timing simulator (PC only), as well as VHDL and Verilog models for use with third-party simulators.