CY3140

The design process in the ABEL environment begins with entering ABEL-HDL (and optional test vectors) using any text editor. The process in Synario is guided by the Project Navigator, and begins with design entry in either schematic, VHDL, or ABEL-HDL. The design can then be functionally simulated at the source-level. It then goes through logic optimization and minimization. The output file then goes into the FLASH370 fitter. Test vectors specified in the ABEL-HDL files are also automatically processed for use in post-fitting device simulation.

The CY3140 fitter generates a JEDEC file for device programming and post-fitting simulation in CYPSIM. The test vectors will also be read in for functional verification.

The post-fitting simulator, CYPSIM, operates under the Windows environment. It takes JEDEC files as input and can read in and write out stimulus files (e.g., test vectors from ABEL-HDL) for functional verification of the design. Users can edit input waveforms graphically and specify simulation length and resolution interactively. Signals can also be grouped, manipulated, and viewed in various formats.