CY6264

Features: * 55, 70 ns access times * CMOS for optimum speed/power* Easy memory expansion with CE1, CE2, and OE fea- tures* TTL-compatible inputs and outputs* Automatic power-down when deselectedPinoutSpecificationsStorage Temperature .................................65°C to +150°CAmbient Temperatu...

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CY6264 Picture
SeekIC No. : 004319466 Detail

CY6264: Features: * 55, 70 ns access times * CMOS for optimum speed/power* Easy memory expansion with CE1, CE2, and OE fea- tures* TTL-compatible inputs and outputs* Automatic power-down when deselectedPino...

floor Price/Ceiling Price

Part Number:
CY6264
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/25

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Product Details

Description



Features:

* 55, 70 ns access times
* CMOS for optimum speed/power
* Easy memory expansion with CE1, CE2 , and OE fea- tures
* TTL-compatible inputs and outputs
* Automatic power-down when deselected



Pinout

  Connection Diagram


Specifications

Storage Temperature .................................65°C to +150°C
Ambient Temperature with
Power Applied.............................................55°C to +125°C
Supply Voltage to Ground Potential..................0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] ............................................0.5V to +7.0V
DC Input Voltage[1].........................................0.5V to +7.0V
Electrical Characteristics Over the Operating Range
Output Current into Outputs (LOW)  .............................20 mA
Static Discharge Voltage    .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current    .................................................... >200 mA



Description

The CY6264 is a high-performance CMOS static RAM orga- nized as 8192 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE1 ), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state drivers. Both devices have an automatic pow-er-down feature (CE1), reducing the power consumption by over 70% when deselected.   The CY6264 is packaged in a 450-mil (300-mil body) SOIC.

An active LOW write enable signal (WE) controls CY6264 the writ- ing/reading operation of the memory. When CE1 and WE in-puts are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0through I/O) is written into the memory  location addressed by the address present on the address pins (A0 through A12). Reading the CY6264 is accomplished by selecting the CY6264 and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location ad- dressed by the information on address pins is present on the eight data input/output pins.

The input/output pins of CY6264 remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A die coat is used to insure alpha immunity.


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