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CY7B9950

Features: • 2.5V or 3.3V operation• Split output bank power supplies• Output frequency range: 6 MHz to 200 MHz• Output-output skew < 100 ps• Cycle-cycle jitter < 100 ps• ± 2% max output duty cycle• Selectable output drive strength• Selectable p...

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SeekIC No. : 004319582 Detail

CY7B9950: Features: • 2.5V or 3.3V operation• Split output bank power supplies• Output frequency range: 6 MHz to 200 MHz• Output-output skew < 100 ps• Cycle-cycle jitter < ...

CY7B9950 Data Sheet

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Part Number:
CY7B9950
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• 2.5V or 3.3V operation
• Split output bank power supplies
• Output frequency range: 6 MHz to 200 MHz
• Output-output skew < 100 ps
• Cycle-cycle jitter < 100 ps
• ± 2% max output duty cycle
• Selectable output drive strength
• Selectable positive or negative edge synchronization
• Eight LVTTL outputs driving 50 terminated lines
• LVCMOS/LVTTL over-voltage-tolerant reference input
• Phase adjustments in 625-/1250-ps steps up to +7.5 ns
• 2x, 4x multiply and (1/2)x, (1/4)x divide ratios
• Spread-Spectrum-compatible
• Industrial temp. range:


Pinout

Connection Diagram


Specifications

Parameter Description Condition Min. Max. Unit
VDD Supply Voltage Functional @ 2.5V ± 5% 2.375 2.625 V
VDD Analog Supply Voltage Functional @ 3.3V ± 10% 2.97 3.63 V
VINmin   Relative to VSS VSS 0.3 - V
VINmax Input Voltage Relative to Vdd - VDD + 0.3 VDC
TS Temperature, Storage Non Functional -65 +150 °C
TA Temperature, Operating Ambient Functional, -40 +85 °C
TJ Temperature, Junction Functional - 155 °C
ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 - V
ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 - 42 °C/W
ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) - 105 °C/W
UL-94 Flammability Rating @1/8 in. V0
MSL Moisture Sensitivity Level 1 ppm



Description

The CY7B9950 RoboClock is a low-voltage, low-power, eight-output, 200-MHz clock driver. It features output phase programmability which is necessary to optimize the timing of high-performance computer and communication systems.

The user can program the phase of the output banks CY7B9950 through nF[0:1] pins. The adjustable phase feature allows the user to skew the outputs to lead or lag the reference clock. Any one of the outputs can be connected to feedback input to achieve different reference frequency multiplication and divide ratios and zero input-output delay.

The CY7B9950 also features split output bank power supplies which enable the user to run two banks (1Qn and 2Qn) at a power supply level different from that of the other two banks(3Qn and 4Qn). Additionally, the three-level PE/HD pin controls the synchronization of the output signals CY7B9950 to either the rising or the falling edge of the reference clock and selects the drive strength of the output buffers. The high drive option (PE/HD = MID) increases the output current from ± 12 mA to ± 24 mA(3.3V).




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