CY7C09579V

The CY7C09569V and CY7C09579V are high-speed 3.3V synchronous CMOS 16K and 32K x 36 dual-port static RAMs. Two ports are provided permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid t_CD2 = 5 ns (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flowthrough mode data will be available t_CD1 = 15 ns after the address is clocked into the device. Pipelined output or flowthrough mode is selected via the FT/Pipe pin.

Each port contains a burst counter on the input address register. The internal write pulse width is independent of the external R/W LOW duration. The internal write pulse is self-timed to allow the shortest possible cycle times.

A HIGH on CE for one clock cycle will power down the internal circuitry to reduce the static power consumption. In the pipelined mode, one cycle is required with CE LOW to reactivate the outputs.

Counter Enable Inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's Address Strobe (ADS). When the port's Count Enable (CNTEN) is asserted, the address counter will increment on each LOW-to-HIGH transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter.

All parts are available in 144-Pin Thin Quad Plastic Flatpack (TQFP) and 172-Ball Ball Grid Array (BGA) packages.