MFG:CYPRESS Package Cooled:800
MFG: CYPRESS
Package Cooled: 800
Description: The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed m...
The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.
The CY7C1031 is designed for Intel® Pentium and i486 CPUbased systems; its counter follows the burst sequence of the Pentium and the i486 processors. The CY7C1032 is architected for processors with linear burst sequences. Burst accesses can be initiated with the processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input.
A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip select input and an asynchronous output enable input provide easy control for bank selection and output three-state control.
CY7C1032
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The CY7C1031-12JC is designed as one kind of 64K by 18 synchronous cache RAM. This device is designed to interface with high-speed microprocessors with minimum glue logic. And is also designed for Intel Pentium and i486 CPU-based systems; CY7C1031-12JC count...
The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and in...
IC SRAM 128X24 ASYNC 119-PBGA
IC SRAM 128X24 ASYNC 119-PBGA
The CY7C1024AV33 is a high-performance CMOS static RAM organized as 131,072 words by 24 bits. Easy memory expansion is provided by an active LOW CE1, CE3, active HIGH CE2, an active LOW Output Enable (OE), and three-state drivers. This device has an automati...
The CY7C1022 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.Writing to the device is accomplished by taking chip enable ...
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