CY7C1316AV18

Features:

• 18-Mb density (2M x 8, 1M x 18, 512K x 36)
• 250-MHz clock for high bandwidth
• 2-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at500 MHz) @ 250 MHz
• Two input clocks (K and K) for precise DDR timing- SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew and flight time mismatching
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4VVDD)
• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball(11x15 matrix)
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement



Application




Specifications


Storage Temperature .................................65°C to +150°C
Ambient Temperature with Power Applied ..55°C to +125°C
Supply Voltage on VDD Relative to GND........ 0.5V to +2.9V
DC Applied to Outputs in High-Z......... 0.5V to VDDQ + 0.5V
DC Input Voltage[9].............................. 0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range[11]



Description


The CY7C1316AV18/CY7C1318AV18/CY7C1320AV18 are1.8V Synchronous Pipelined SRAM equipped with DDR-IIarchitecture. The DDR-II consists of an SRAM core withadvanced synchronous peripheral circuitry and a 1-bit burstcounter. Addresses for Read and Write are latched onalternate rising edges of the input (K) clock. Write data is registeredon the rising edges of both K and K. Read data is drivenon the rising edges of C and C if provided, or on the rising edgeof K and K if C/C are not provided. Each address location isassociated with two 8-bit words in the case of CY7C1316AV18that burst sequentially into or out of the device. The burstcounter always starts with a "0" internally in the case ofCY7C1316AV18. On CY7C1318AV18 and CY7C1320AV18,the burst counter takes in the least significant bit of the externaladdress and bursts two 18-bit words in the case ofCY7C1318AV18 and two 36-bit words in the case ofCY7C1320AV18 sequentially into or out of the device.Asynchronous inputs of CY7C1316AV18/CY7C1318AV18/CY7C1320AV18 include impedance match (ZQ).Synchronous data outputs (Q, sharing the same physical pinsas the data inputs D) are tightly matched to the two output echoclocks CQ/CQ, eliminating the need for separately capturingdata from each individual DDR SRAM in the system design.Output data clocks (C/C) enable maximum system clockingand data synchronization flexibility.All synchronous inputs pass through input registers controlledby the K or K input clocks. All data outputs of CY7C1316AV18/CY7C1318AV18/CY7C1320AV18 pass through outputregisters controlled by the C or C input clocks. Writes areconducted with on-chip synchronous self-timed write circuitry.