CY7C1320BV18

The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1316BV18 and two 9-bit words in the case of CY7C1916BV18 that burst sequentially into or out of the device. The burst counter always starts with a "0" internally in the case of CY7C1316BV18 and CY7C1916BV18. On CY7C1318BV18 and CY7C1320BV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1318BV18 and two 36-bit words in the case of CY7C1320BV18 sequentially into or out of the device.

Asynchronous inputs of CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 include output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for
separately capturing data from each individual DDR SRAM CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility.

All synchronous inputs of CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.