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CY7C1331

Features: • Supports 66-MHz Pentium™ processor cache systems with zero wait states• Single 3.3V power supply• 64K by 18 common I/O• Fast clock-to-output times -8.5 ns• Two-bit wraparound counter supporting the Pentium and 486 burst sequence (7C1331)• Two-b...

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SeekIC No. : 004319937 Detail

CY7C1331: Features: • Supports 66-MHz Pentium™ processor cache systems with zero wait states• Single 3.3V power supply• 64K by 18 common I/O• Fast clock-to-output times -8.5 ns&#...

CY7C1331 Data Sheet

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Part Number:
CY7C1331
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Supports 66-MHz Pentium™ processor cache systems with zero wait states
• Single 3.3V power supply
• 64K by 18 common I/O
• Fast clock-to-output times
   -8.5 ns
• Two-bit wraparound counter supporting the Pentium and 486 burst sequence (7C1331)
• Two-bit wraparound counter supporting linear burst sequence (7C1332)
• Separate processor and controller address strobes
• Synchronous self-timed write
• Direct interface with the processor and external cache controller
• Asynchronous output enable
• JEDEC-standard pinout
• 52-pin PLCC and PQFP packaging


Pinout

Connection Diagram


Specifications

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..........................65°C to +150°C
Ambient Temperature with
Power Applied......................................55°C to +125°C
Supply Voltage on VCC Relative to GND......0.5V to +3.6V
DC Voltage Applied to Outputs
in High Z State[2]................................0.5V to VCC + 0.3V
DC Input Voltage[2] ...........................0.5V to VCC + 0.3V
Current into Outputs (LOW) ......................................20 mA
Static Discharge Voltage ........................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................  >200 mA


Description

The CY7C1331 and CY7C1332 are 3.3V 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter CY7C1331 and CY7C1332 captures the first address in a burst and increments the address automatically for the rest of the burst access.

The CY7C1331 is designed for Intel Pentium and i486 CPU-based systems; its counter follows the burst sequence of the Pentium and the i486 processors. The CY7C1332 is architected for processors with linear burst sequences. Burst accesses can be initiated with the processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input.

A synchronous self-timed write mechanism CY7C1331 and CY7C1332 is provided to simplify the write interface. A synchronous chip select input and an asynchronous output enable input provide easy control for bank selection and output three-state control.




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