CY7C1333

The CY7C1333 is a 3.3V, 64K by 32 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1333 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. The CY7C1333 is pin/functionally compatible to ZBT SRAM MT55L64L32F.

All synchronous inputs of CY7C1333 pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which, when deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 12.0 ns (66-MHz device).

Write operations of CY7C1333 are controlled by the four Byte Write Select (BWS_[0:3]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE₁, CE₂, CE₃) CY7C1333 and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers of CY7C1333 are synchronously three-stated during the data portion of a write sequence.