CY7C1336F

The CY7C1336F is a 65,536 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs of CY7C1336F are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs of CY7C1336F include all addresses, all data inputs, address-pipelining Chip Enable (CE₁), depth-expansion Chip Enables (CE₂ and CE₃), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW_[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

The CY7C1336F allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses of CY7C1336F can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input.

Addresses and chip CY7C1336F enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).

The CY7C1336F operates from a +3.3V core power supply
while all outputs may operate with a +3.3V supply. All inputs
and outputs are JEDEC-standard JESD8-5-compatible.