CY7C1337

Features: • Low (660 mW) standby power (f=0, L version)• Supports 117-MHz bus operations with zero wait states• Fully registered inputs and outputs for pipelined operation• 32K x 32 common I/O architecture• 3.3V VDD and 2.5V VDDQ for 2.5V I/Os• Fast Clock-to-out...

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CY7C1337 Picture
SeekIC No. : 004319945 Detail

CY7C1337: Features: • Low (660 mW) standby power (f=0, L version)• Supports 117-MHz bus operations with zero wait states• Fully registered inputs and outputs for pipelined operation• 3...

floor Price/Ceiling Price

Part Number:
CY7C1337
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/28

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Product Details

Description



Features:

• Low (660 mW) standby power (f=0, L version)
• Supports 117-MHz bus operations with zero wait states
• Fully registered inputs and outputs for pipelined operation
• 32K x 32 common I/O architecture
• 3.3V VDD and 2.5V VDDQ for 2.5V I/Os
• Fast Clock-to-output times
   -5.0 ns (for 117-MHz device)
   -5.5 ns (for 100-MHz device)
   -8.5 ns (for 66-MHz device)
• User-selectable burst counter supporting interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP pinout
• "ZZ" Sleep Mode option
• Supports Stop Clock option for power conservation



Pinout

  Connection Diagram


Specifications

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................ -65°C to +150°C
Ambient Temperature with
Power Applied........................................ -55°C to +125°C
Supply Voltage on VDD Relative to GND.........-0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State[7]]...............................-0.5V to VDDQ + 0.5V
DC Input Voltage[7].............................-0.5V to VDDQ + 0.5V
Current into Outputs (LOW)....................................... 20 mA
Static Discharge Voltage ......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA



Description

The CY7C1337 is 3.3V 32K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic.

All synchronous inputs of CY7C1337 pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 5ns (117 MHz version). A 2-bit on-chip wraparound burst counter CY7C1337 captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.

The CY7C1337 supports either the interleaved burst sequence or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the processor address strobe (ADSP) or the controller address strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. Byte write operations CY7C1337 are qualified with the four Byte Write Select (BW[0-3]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes CY7C1337 are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous chip of CY7C1337 selects (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first clock of a read cycle when going from a deselected to a selected state.




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