MFG:CY Package Cooled:TQFP D/C:529
MFG: CY
Package Cooled: TQFP
D/C: 529
Description: The CY7C1338 is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed micropr...
The CY7C1338 is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.
The CY7C1338 allows both interleaved and linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input.
A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip enable input and an asynchronous output enable input provide easy control for bank selection and output three-state control.
CY7C1338
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The CY7C1337 is 3.3V 32K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic.All synchronous inputs of CY7C1337pass through input registers controlled by the rising edge of the clock. All data ou...
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The CY7C1336 is a 3.3V 64K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit On-Chip Counter CY7C1336captures the first address...
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