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CY7C1338

Features: • Supports 117-MHz microprocessor cache systems with zero wait states• 128K by 32 common I/O• Fast clock-to-output times -7.5 ns (117-MHz version)• Two-bit wraparound counter supporting either interleaved or linear burst sequence• Separate processor and cont...

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SeekIC No. : 004319946 Detail

CY7C1338: Features: • Supports 117-MHz microprocessor cache systems with zero wait states• 128K by 32 common I/O• Fast clock-to-output times -7.5 ns (117-MHz version)• Two-bit wraparou...

CY7C1338 Data Sheet

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Part Number:
CY7C1338
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Supports 117-MHz microprocessor cache systems with zero wait states
• 128K by 32 common I/O
• Fast clock-to-output times
   -7.5 ns (117-MHz version)
• Two-bit wraparound counter supporting either interleaved or linear burst sequence
• Separate processor and controller address strobes provide direct interface with the processor and external cache controller
• Synchronous self-timed write
• Asynchronous output enable
• 3.3V I/Os
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ "sleep" mode


Pinout

Connection Diagram


Specifications

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ...................................65°C to +150°C
Ambient Temperature with
Power Applied...............................................55°C to +125°C
Supply Voltage on VDD Relative to GND................0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State[5]...............................................0.5V to VDD + 0.5V
DC Input Voltage[5]........................................... 0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA


Description

The CY7C1338 is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter CY7C1338 captures the first address in a burst and increments the address automatically for the rest of the burst access.

The CY7C1338 allows both interleaved and linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses of CY7C1338 can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input.

A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip of CY7C1338 enable input and an asynchronous output enable input provide easy control for bank selection and output three-state control.




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