CY7C1338G

The CY7C1338G is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum a ccess delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automati- cally for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable(CE₁</a>), depth-expansion Chip Enables (CE₂</a> and CE₃</a>), Burst Control inputs (ADSC</a>, ADSP</a>, and ADV</a>), Write Enables(BW</a>_[A:D], and BWE</a>), and Global Write (GW</a>). Asynchronousinputs include the Output Enable (OE</a>) and the ZZ pin.

The CY7C1338G allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses  can be initiated with the Processor Address Strobe (ADSP</a>) or the cache Controller Address Strobe (ADSC</a>) inputs. Address advancement is controlled by the Address Advancement (ADV</a>) input.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP</a>) or Address Strobe Controller(ADSC</a>) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV</a>).

The CY7C1338G operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.